1. Field of the Invention
The present invention relates in general to clock generators, and more particularly to clock generator using a comparator and which compensates for comparator error, including comparator delay and input offset voltage, to improve accuracy of the clock signal frequency.
2. Description of the Related Art
A clock generator is a circuit that produces a clock or timing signal for use in synchronizing circuit operation. Although various different types of clock generators are known, the use of a comparator in the generation of a clock signal is a common configuration. A schematic diagram of a clock generator 100 configured according to a conventional scheme is illustrated in FIG. 1 for developing a sawtooth waveform. A current source 102 coupled to a first supply voltage generates a charge current ICHG which is provided to an oscillation capacitor COSC. The capacitor COSC is coupled between a charge node 104 and a second supply voltage and develops a charge voltage VC on the charge node 104. The first supply voltage is shown herein as VDD and may have any suitable voltage level (positive or negative) relative to the second supply voltage. The second supply voltage is shown herein as VSS and may have any suitable positive, negative or ground voltage level and may be considered as a reference voltage relative to the first supply voltage. VC is provided to a positive input of a comparator 106, which receives a reference voltage VREF at a negative input. As used herein, comparators and amplifiers are described as having positive and negative inputs, where it is understood that the inputs may alternatively be referred to as having non-inverting and inverting inputs, respectively. The comparator (COMP) 106 develops a compare signal CMP at its output, which is provided to an input of a “positive” (POS) one-shot device 108. The POS one-shot device 108 device outputs a discharge signal DCH to a control input of a normally-open switch S1. The POS one-shot device 108 asserts a pulse on the DCH signal in response to a “positive” or rising edge of CMP. The switch S1 has its current terminals coupled in parallel with the capacitor COSC between node 104 and VSS.
FIG. 2 is a timing diagram illustrating operation of the clock generator 100, in which the charge voltage VC and the discharge signal DCH are plotted versus time. At an initial time t0, the voltage of the capacitor COSC is zero so that VC is at VSS. Also at time t0, DCH is low (or logic “0”), the switch S1 is open, and the output of COMP 106, CMP, is also low since VC is less than the reference voltage VREF. The relatively constant charge current ICHG from the current source 102 flows into the capacitor COSC which causes VC to ramp up at a relatively constant rate. VC reaches VREF at a subsequent time t1. COMP 106, however, does not transition CMP at time t1. Instead, after VC reaches VREF and after a delay through COMP 106, it asserts CMP high at a subsequent time t2 which then triggers the one-shot device 108 to pulse DCH high. The one-shot device 108 pulses DCH high and then back low in response to CMP going high, so that DCH goes low at a subsequent time t3. The DCH signal pulsing high momentarily closes the switch S1 to discharge the capacitor COSC so that VC goes back to VSS at or just before time t3. At about time t3, DCH is back low so that switch S1 is re-opened, and the cycle repeats. In this manner, VC oscillates at a relatively constant rate and develops the sawtooth waveform which may be used as a clock signal or otherwise provided to additional clock circuitry (not shown).
The oscillation period, TOSC, of the clock generator 100 is intended to be TC, which is the time the ramping voltage VC rises from its low reset point at VSS to the reference voltage VREF. TC is intended, therefore, to be dependent primarily on the capacitance of COSC, the magnitude of the charge current ICHG, and the voltage level of VREF. The one-shot device 108 adds a short delay time TW which is the width of each DCH pulse. The one-shot device 108 is easily configured to pulse DCH very quickly so that TW<<TC, so that TW is very small and adds only a negligible amount of error. Also, the switch S1 is configured sufficiently large relative to the capacitance of COSC so that COSC is completely discharged relatively quickly within the delay time TW of the DCH pulse, so that there is little or no additional delay caused by discharging the capacitor COSC.
The relative speed of COMP 106, however, is more difficult to control and is a significant contributor of error for relatively high oscillation frequency and/or low bias current of the comparator 106. Furthermore, temperature changes causing speed variations are difficult to reduce or otherwise eliminate. As shown in FIG. 2, after VC reaches VREF, VC continues to increase while COMP 106 is switching, resulting in an additional switching delay time of TS to the overall period. VC thus toggles between VSS and an overshoot voltage VOVR in which VOVR=VREF+VOFF, where VOFF is an offset voltage caused by the additional switching delay time TS of the comparator 106. The actual period of oscillation is TOSC≈TC+TS in which TS, the switching delay of the comparator 106, is an error value which causes an inaccurate period of the sawtooth waveform. The increase in error results in an undesired decrease of the intended or target frequency. It is desired to minimize or otherwise eliminate the switching delay TS of COMP 106.
Another source of comparator error is the input offset voltage of the comparator. The input offset voltage causes the comparator to switch at a different point from VC=VREF even if, solely for purposes of illustration, the comparator error is assumed to be zero. For example, if COMP 106 has an input offset voltage VINOFF (and again assuming zero switching delay), then it switches when VC=VREF+VINOFF rather than when VC=VREF. It is noted that VINOFF is just as likely to be positive or negative for a given comparator so that the input offset voltage error must be added to the delay error to determine the overall error of the comparator. Although not specifically shown, the input offset voltage contributes to the overall comparator error in substantially similar manner as the delay error, so that the actual frequency of the clock generator 100 is difficult to control or predict for a given implementation.
Various conventional methods may be used to reduce the input offset voltage of a comparator. One method is to measure the offset and then use trimming techniques or the like to compensate for the measured offset. Such techniques, however, consume valuable time and manufacturing resources and add substantially to manufacturing cost. Another technique is to increase gain by increasing bias current which tends to reduce the input offset. Increasing gain, however, results in an significant increase in power consumption and does not necessarily eliminate the input offset voltage.
A schematic diagram of a clock generator 300 configured according to another conventional scheme is illustrated in FIG. 3 for developing a triangular waveform. The current source 302 coupled to VDD generates the charge current ICHG which is provided through a second, normally-closed switch S1B to an oscillation capacitor COSC. The capacitor COSC is coupled between a charge node 304 and VSS and develops the charge voltage VC on the charge node 304. The switch S1B has current terminals coupled between the current source 302 and node 304. COMP 106 is replaced by a pair of comparators COMP1 306 and COMP2 310. VC is provided to the positive input of COMP1 306 and to the negative input of COMP2 310. The negative input of COMP1 306 receives a first reference voltage VREF1 and the positive input of COMP2 receives a second reference voltage VREF2. COMP1 develops a set signal “S” at its output which is provided to a set (S) input of a set-reset (SR) latch 308. COMP2 develops a reset signal “R” at its output which is provided to a reset (R) input of the SR latch 308. The Q output of the SR latch 308 device provides a discharge signal DCH which is provided to the inverting control input of the switch S1B and to the control input of a normally-open switch S1A. S1A has current terminals coupled between node 304 and an input of a current sink 312, which as its output coupled to VSS. The current sink 312 develops a discharge current IDCHG for discharging COSC when closed.
FIG. 4 is a timing diagram illustrating operation of the clock generator 300, in which the charge voltage VC and the S, R and DCH signals are plotted versus time. At an initial time t0, the voltage of VC has decreased below a lower threshold voltage level determined by VREF2, so that COMP2 310 asserts R high to reset the SR latch 308. DCH, which was high from a prior cycle, goes low at about time t0 closing switch S1B and opening switch S1A. The discharge current IDCHG from the current sink 312 is thus removed from COSC whereas switch S1B closes so that the charge current ICHG from current source 302 begins charging COSC. VC thus ramps up at a rate determined by the capacitance of COSC and the level of the charge current ICHG. When COMP2 310 sense VC above VREF2, it asserts R back low at about time t1.
At subsequent time t2, VC reaches an upper threshold voltage level determined by VREF1. At subsequent time t3 after a switching delay TS1A from time t2, COMP1 306 asserts S high to set the SR latch 308 pulling DCH back high. In response to DCH going high, switch S1B opens removing ICHG from COSC and switch S1A closes so that the discharge current IDCHG begins discharging COSC. VC thus ramps back down at a rate determined by the capacitance of COSC and the level of the discharge current IDCHG. At about time t4 after a delay of TS1B from time t3, VC crosses VREF1 as it continues to ramp down. When COMP1 306 detects that VC is below VREF1, it asserts S back low at subsequent time t5. At subsequent time t6, VC falls back down to VREF2 once again. At subsequent time t7 after a switching delay TS2A from time t6, COMP2 310 asserts R back high again to reset the SR latch 308 pulling DCH back low to close switch S1B and to open switch S1A. VC begins ramping back up, and at about time t8 after a delay of TS2B from time t7, VC crosses VREF2 as it continues to ramp up.
Operation repeats in this manner so that VC oscillates at a relatively constant rate and develops the triangular waveform which may be used as a clock signal or otherwise provided to additional clock circuitry (not shown). VC toggles relative to the threshold voltages VREF1 and VREF2 at a duty cycle based on the relative values of ICHG and IDCHG. The clock generator 300 exhibits similar inaccuracies as the clock generator 100, however, due to comparator switching delays of COMP1 306 and COMP2 310.
VC is intended to toggle between VREF1 and VREF2, shown as a rising period TC1 and a falling period TC2. The desired period of oscillation is desired to be TOSC=TC1+TC2. In actual operation, however, VC rises above VREF1 and falls below VREF2 every cycle. The delay of the comparator 306 causes a significant delay of TS1A+TS1B at the peak of the triangular waveform, and the delay of the comparator 310 causes another significant delay of TS2A+TS2B at the valley of the triangular waveform. The actual period of oscillation is TOSC=TC1+TC2+TS1A+TS1B+TS2A+TS2B, which is significantly greater than the desired period. In this manner, the overall period of the resulting triangular waveform is significantly greater than intended so that the target frequency is correspondingly reduced. In a similar manner previously described for the comparator 106, it is desired to minimize or otherwise eliminate the switching delays of the comparators 306 and 310.
COMP1 306 and COMP2 310 further introduce input offset voltage error in a similar manner described for COMP 106. In the same manner, the input offset voltage of each comparator contributes to the overall comparator error in substantially similar manner as the delay error, so that the actual frequency of the clock generator 300 is also difficult to control or predict for a given implementation. The conventional methods to compensate for the input offset voltage either consume valuable resources and increase overall cost or substantially increase power consumption.